Responsibility

• The role will involve the CPLD and FPGA designs, Research, HDL development, simulations, synthesis, and lab integration.
• Works with a global team of engineers.
• The Engineer FPGA / ASIC Intern
  may support different phase of the design life cycle including requirements definition, detailed design, validation of requirements and verification of implementation.

Your qualifications

• Good communication/writing skills in German & English
• Ongoing bachelor's or master's degree in Electronics, Microelectronics and Control or similar
• First professional experience in personnel or applicant management is an advantage
• Structured way of working as well as pronounced quality awareness
• Communicative personality and team spirit

What we offer

• Food Voucher
• Remote Working
• Flexible time to match your study
• Full opportunity to broaden your horizons and expand your professional expertise
• Part-time work, research and learning can later be increased to 38h/week
• Salary up to EUR 1.622,45

We look forward to your detailed application including a possible start date.