ML based Error Pattern Detection for SoC Register Verification based on UVM Register Model

Description 

Nowadays, the Universal Verification Methodology (UVM) is the de facto standard for verification environments used to verify today’s System on Chips (SoC). Each SoC contains hundreds of configuration and status registers which require special attention during the verification process. A set of dedicated classes, called UVM RAL (Register Abstraction Layer), targets the verification of these registers. Although UVM RAL is indented to model and verify the implementation of registers it lacks support for error pattern analysis and debugging. 

Target of the Scientific Work is to develop data, address and time aware machine learning (ML) based algorithms for detecting common error pattern leading to a significant debug time reduction. The reporting needs to be done in textual and graphical ways. The algorithms should address common error pattern like bitfield misalignments and addressing issues. The developed algorithm will be integrating into the existing ErrorAnalyzer environment. 

Tasks 

The Scientific Work comprises of the following tasks 

• Develop appropriate fault models for SoC configuration registers 
• Develop ML based algorithm for detecting common error pattern 
• Integrate the developed algorithm into the UVM verification environment 

Required Skills 

As an ideal candidate for the Master Thesis you have the following skills 

• Good programming skills (C/C++, Python) 
• Basic knowledge on digital verification (SystemVerilog / UVM) 
• Basic understanding of digital design 
• Interest in developing Machine Learning Algorithms 

Organizational 

• Start date: Now 
• Duration: 5-6 months (part time) 
• Location: Graz 

Contact 

If you are attracted by the topic of the Scientific Work and you want to be part of an innovative and dynamic team, send your application to the following email address: klaus.strohmayer@semify-eda.com